There are different methods of incorporating capacitors into an integrated electronic circuit. Certain methods lead to the fabrication of a capacitor fitted with metallic electrodes parallel to the main plane of the substrate, and of which the upper electrode is located, for example, in the last metallic interconnection levels. Such a capacitor, in order to have a high capacity, occupies a portion of the surface area projected onto the substrate that is just as high. The resulting size makes it more difficult to incorporate metallic tracks and vias in the interconnection layers.
Capacitors with “vertical” electrodes, of which the electrodes are orthogonal to the main plane of the substrate, have also been made. These capacitors are generally formed using a Damascene type process, by filling trenches with a MIM stack comprising a thin metallic layer, a thin insulating layer and another thin metallic layer. These capacitors generally have a limited capacity.
In FIG. 1, a micro-electronic device fitted with at least one 3 dimensional MIM (Metal-Insulator-Metal) capacitor called “3D MIM” is illustrated. This device is fitted with at least one 3 dimensional capacitor designed both to satisfy the demands in terms of its reduced size and high capacity. This capacitor features portions of electrodes orthogonal to the main plane of the substrate and portions of electrodes parallel to the main plane of the substrate.
The device is formed from a substrate 1, on which a plurality of components and superposed metallic interconnection levels, for example 6 metallic interconnection levels L1, L2, L3, L4, L5, L6 (the components and the 4 first metallic interconnection levels L1, . . . , L4, which are shown diagrammatically in FIG. 1 by a block in dotted lines above the substrate 1) have been created. This capacitor 2 is fitted with a first electrode featuring a “vertical” section formed in a plane that is orthogonal to the main plane of the substrate 1, from a first thin metallic layer 3, a second electrode featuring a “vertical” section formed in a plane orthogonal to the main plane of the substrate 1, from a second thin metallic layer 5 separated from the first thin metallic layer 3 by a thin layer of dielectric material 4, wherein the first thin metallic layer 3, the thin dielectric layer 4 and the second thin metallic layer 5 cover the walls. The bottom of the trenches is made in an insulating layer 6 in which metallic vias 7 connecting the fifth metallic level L5 and the sixth metallic level L6 are created. The electrodes of the capacitor also feature sections of horizontal electrodes formed at the bottom of the trenches from metallic layers 3 and 5 between the metallic layers 8 and 9 respectively of the 5th level and 6th level.
The metallic layer 8, on which the MIM stack rests at the bottom of the trenches, is generally copper based. When creating this metallic layer 8, the copper induces stresses which tend to cause, after the copper is deposited, the formation of hillocks on the surface of this metallic section 8. These hillocks tend to cause manufacturing defects in sections of the device located above the 5th metal level and to downgrade the electrical performances of the MIM capacitor, especially in terms of breakdown voltage.
The defects caused are furthermore greater the larger the surface of the metallic section 8.
There is the issue of improving the capacity of the integrated MIM 3 dimensional capacitors, while conserving a satisfactory integration density in the integrated circuit in which these capacitors are made. Furthermore, there is the issue of reducing the number of defects in the integrated circuits fitted with MIM capacitors.